SH-2A Datasheet, PDF (465/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(4) FPUL Store Instruction (STS.L)
Instruction Type
STS.L FPUL,@-Rn
Section 8 Pipeline Operation
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
: CPU pipeline
IF DF EX NA
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF ⋅ ⋅ ⋅
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF ⋅ ⋅ ⋅
: FPU pipeline
Operation
The CPU pipeline ends after four stages – IF, ID, EX, MA – and the FPU pipeline after four stages
– IF, DF, EX, NA.
Instruction Issuance
This instruction uses the FPU load/store pipeline and memory access pipeline.
If FPUL is waiting for the result of an FPU arithmetic operation, the latency of the previous
instruction is reduced by 1. See section 8.6, Contention Due to FPU, for details.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 451 of 484
REJ09B0051-0300