SH-2A Datasheet, PDF (488/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Operation
• Single-Precision
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after four stages
– IF, DF, E1, E2. As the T bit is checked in E2, an instruction that references the T bit
immediately afterward is stalled for 2 cycles.
FCMP
BT
IF ID EX
IF DF E1 E2
IF — — ID EX
IF — — DF ⋅ ⋅ ⋅
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline
Operation
• Double-Precision
The CPU pipeline ends after four stages – IF, ID, EX, EX – and the FPU pipeline after five
stages – IF, DF, E1, E1, E2. As the T bit is checked in E2, an instruction that references the T
bit immediately afterward is stalled for 3 cycles.
FCMP
BT
IF ID EX
: CPU pipeline
IF DF E1 E1 E2
: FPU pipeline
IF — — — ID EX : CPU pipeline
IF — — — DF ⋅ ⋅ ⋅ : FPU pipeline
Instruction Issuance
These instructions use the FPU arithmetic operation pipeline.
Parallel Execution Capability
Parallel execution of a double-precision FCMP instruction and the following instruction is not
possible.
Rev. 3.00 Jul 08, 2005 page 474 of 484
REJ09B0051-0300