SH-2A Datasheet, PDF (369/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
When the FPSCR value is read using an STS or STS.L instruction, FPSCR is read after
completion of the previously issued operation. As a result, execution is delayed by an interval of
[latency of preceding operation + 1 slot] (figure 8.41).
Instruction 1 (single-precision)
(FADD FR6,FR9)
Instruction 2
(STS FPSCR,R3)
IF DF E1 E2 SF
IF — — — DF EX NA SF
Figure 8.41 Example of Reading FPSCR
Double-precision floating-point arithmetic operation instructions (FADD, FSUB, FMUL) require
6 cycles for the E1 stage. Another floating-point arithmetic operation instruction will not enter the
E1 stage during this interval. If another floating-point arithmetic operation instruction appears
before a double-precision floating-point arithmetic operation instruction finishes the E1 stage, that
floating-point arithmetic operation instruction has its execution delayed by a predetermined slot
interval, and enters the E1 stage after the double-precision floating-point arithmetic operation
instruction has finished the E1 stage. A floating-point load/store instruction arriving during this
interval can be executed (figure 8.42).
FADD DR4,DR6
FABS DR0
STS FPUL,R0
FMUL DR2,DR0
IF DF E1 E1 E1 E1 E1 E1 E2 SF
IF DF EX NA SF
IF DF EX NA
IF — — — — — DF E1 E2 SF
Figure 8.42 Example of Double-Precision FPU Operation and Next FPU Instruction
With an FDIV or FSQRT instruction, after the E1 stage is used in initialization, operation is
performed by an independent computer (ED stage), after which the operation result is written
back. A floating-point arithmetic operation instruction following either of these instructions
operates as described below. See section 8.9, Pipeline Operations for Each Instruction, for the
kind of pipeline used with each instruction.
(1) During E1 stage use in initialization, another floating-point arithmetic operation instruction
will not enter the E1 stage. Other instructions enter the E1 stage after FDIV or FSQRT
initialization ends.
(2) After an FDIV or FSQRT instruction has progressed to the ED stage, an FPU instruction is
executed without delay unless it uses the FDIV or FSQRT instruction result register (figure
8.40).
Rev. 3.00 Jul 08, 2005 page 355 of 484
REJ09B0051-0300