SH-2A Datasheet, PDF (381/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
Data
Memory
4
transfer store
instructions instructions
1
0 • These instruc- MOV.B Rm,@Rn
tions use the
memory access
MOV.W
Rm,@Rn
pipeline.
MOV.L Rm,@Rn
1
MOV.B Rm,@-Rn
MOV.W Rm,@-Rn
MOV.L Rm,@-Rn
MOV.B R0,@Rn+
MOV.W R0,@Rn+
MOV.L R0,@Rn+
0
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
MOV.L Rm,@(R0,Rn)
MOV.B R0,@(disp,GBR)
MOV.W R0,@(disp,GBR)
MOV.L R0,@(disp,GBR)
4 to 19 1 to 16 1 to 16
MOVML.L Rm,@-R15
MOVMU.L Rm,@-R15
4
1
0 • These are 32-bit MOV.B Rm,@(disp12,Rn)
instructions.
MOV.W Rm,@(disp12,Rn)
• These instruc-
tions use the
MOV.L
Rm,@(disp12,Rn)
memory access
pipeline.
PREF
4
instruction
1
0 • This instruction PREF @Rm
uses the
memory access
pipeline.
Rev. 3.00 Jul 08, 2005 page 367 of 484
REJ09B0051-0300