SH-2A Datasheet, PDF (384/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
Bit
Register-
3
manipula- register bit
tion
operation
instructions instructions
1
1
—
BLD #imm3,Rn
BSET #imm3,Rn
BCLR #imm3,Rn
BST #imm3,Rn
Memory-
5
T-bit bit
operation
instructions
3
3 • These are 32-bit BAND.B #imm3,@(disp12,Rn)
instructions.
• These instruc-
tions use the
memory access
pipeline.
BANDNOT.B
#imm3,@(disp12,Rn)
BOR.B #imm3,@(disp12,Rn)
BORNOT.B
#imm3,@(disp12,Rn)
BLD.B #imm3,@(disp12,Rn)
BLDNOT.B
#imm3,@(disp12,Rn)
BXOR.B #imm3,@(disp12,Rn)
Memory bit
6
manipula-
tion
instructions
3
2
BST.B #imm3,@(disp12,Rn)
BCLR.B #imm3,@(disp12,Rn)
BSET.B #imm3,@(disp12,Rn)
Shift
Shift
3
instructions instructions
1
1 • These instruc- ROTL Rn
tions use the
shift pipeline.
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAL Rn
SHAR Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
SHAD Rm,Rn
SHLD Rm,Rn
Rev. 3.00 Jul 08, 2005 page 370 of 484
REJ09B0051-0300