SH-2A Datasheet, PDF (291/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.5.2
FADD
Floating-Point
Addition
Floating-point ADD
Section 6 Instruction Descriptions
Floating-Point Instruction
PR Format
Abstract
0
FADD FRm,FRn FRn+FRm → FRn
1
FADD DRm,DRn DRn+DRm → DRn
Code
Cycle
1111nnnnmmmm0000 1
1111nnn0mmm00000 6
T Bit
—
—
Description
When FPSCR.PR = 0: Arithmetically adds the two single-precision floating-point numbers in FRn
and FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically adds the two double-precision floating-point numbers in
DRn and DRm, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FADD (int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else if((data_type_of(m) == DENORM) ||
(data_type_of(n) == DENORM)) set_E();
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case NORM: normal_faddsub(m,n,ADD); break;
case PZERO:
Rev. 3.00 Jul 08, 2005 page 277 of 484
REJ09B0051-0300