SH-2A Datasheet, PDF (447/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

(10) MAC → Register Transfer Instructions
Instruction Types
STS MACH,Rn
STS MACL,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Section 8 Pipeline Operation
Operation
The pipeline ends after four stages: IF, ID, EX, WB.
See section 8.7, Contention Due to Multiplier, for general pipeline details. These instructions
have one execution slot, a latency of two, and zero lock state. Detailed examples where there are
consecutive instructions relating to the pipeline of this instruction or the multiplier are given
below.
(a) When an STS instruction is immediately followed by a MAC.W or MAC.L instruction
There is no multiplier contention.
STS MACH,Rn
MAC.W @Rm+,@Rn+
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
IF ID EX MA MA mm mm
IF — ID EX ⋅ ⋅ ⋅
Rev. 3.00 Jul 08, 2005 page 433 of 484
REJ09B0051-0300