SH-2A Datasheet, PDF (6/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page
7.4.2 Register Bank 330
Addressing
Figure 7.4 Register 331
Bank Addressing
8.2 Slots and
339
Pipeline Flow
Figure 8.3
Impossible Pipeline
Flow (1)
8.6 Contention Due 353
to FPU
Figure 8.36
Example of Use of
Result of Zero-
Latency Instruction
as Source
8.9 Pipeline
372
Operations for Each
Instruction
Table 8.1 Number
of Instruction Stages
and Execution States
Appendix A SH- 480,
2A/SH2A-FPU
481
Parallel Execution
Revision (See Manual for Details)
Description amended
⋅⋅⋅ and the entry within the bank (R0 to R14, GBR, MACH, MACL,
PR, VTO) is specified by address bits 6 to 2 (EN).
Figure amended
(Before) IVO → (After) VTO
Figure amended
Instruction 1 IF ID EX MA WB
Figure amended
(Before) GX → (After) EX
Table amended
Type
Category
Number
of Stages
Execution
States
Latency
Contention
System MAC →
4
control
register
instructions transfer
instructions
1
2 • These instruc-
tions use the
multiplication
result read path.
STS
STS
Instructions
MACH,Rn
MACL,Rn
Table amended
Classifi- Classifi-
cation of cation of
First
Second
Instruction Instruction
MW
MW
STC.L
VBR,@-Rn
Instruction
STS.L
PR,@-Rn
EX
EX
SUBC
Rm,Rn
SUBV
Rm,Rn
BR
MR
JSR/N
@@(disp8,TBR)
TST
#imm,R0
Rev. 3.00 Jul 08, 2005 page vi of xiv