SH-2A Datasheet, PDF (452/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(13) RESBANK Instruction
Instruction Type
RESBANK
Pipeline
• When B0 == 0
Instruction A
Next instruction
• When B0 == 1
Instruction A
Next instruction
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX EX EX EX EX EX EX EX
IF — — — — — — — — ID EX ⋅ ⋅ ⋅
↔ ↔ ↔ ↔ ↔ ↔ ⋅⋅⋅
IF ID EX MA MA MA ⋅ ⋅ ⋅
IF — — — — — ⋅ ⋅ ⋅
↔ ↔ ↔ Slots
MA MA MA WB
ID EX ⋅ ⋅ ⋅
Operation
The operation is different when the BO bit is 0 and when the BO bit is 1.
When the BO bit is 0, restoration from a bank is performed. The pipeline comprises IF and ID
followed by EX, EX, EX, EX, EX, EX, EX (nine repetitions of EX), and ends after 11 stages.
During this time, register restoration from the bank is performed.
When the BO bit is 1, restoration from the stack is performed. The pipeline comprises IF, ID, and
EX, followed by MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA,
MA, MA, MA, MA, (19 repetitions of MA), followed by WB, and ends after 23 stages.
Instruction Issuance
When the BO bit is 0, this instruction does not cause resource contention.
When the BO bit is 1, this instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 438 of 484
REJ09B0051-0300