SH-2A Datasheet, PDF (104/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.2
BANDNOT
Bit ANDNOT
Bit NOT Logical AND
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
BANDNOT.B #imm3,
@(disp12,Rn)
Abstract
Code
Cycle T Bit
~ (<imm> of (disp+Rn)) & T 0011nnnn0iii10011100dddddddddddd 3
→T
Operation
result
Description
ANDs the value obtained by inverting a specified bit of memory at the address indicated by (disp
+ Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit
immediate data. With this instruction, data is read from memory as a byte unit.
BANDNOT.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
Inversion
T
&
T
Operation
BANDNOTM (long d, long i, long n) /*BANDNOT.B #imm3, @(disp12, Rn) */
{
long disp, imm, temp, assignbit;
disp = (0x00000FFF & (long)d);
imm= (0x00000007&(long)i);
temp= (long) Read_Byte (R[n]+disp);
assignbit =(0x00000001<<imm)&temp;
if((T==1)&&(assignbit==0)) T=1;
else T=0;
PC+=4;
}
Rev. 3.00 Jul 08, 2005 page 90 of 484
REJ09B0051-0300