SH-2A Datasheet, PDF (406/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(2) Multiply-and-Accumulate Instruction
Instruction Type
MAC.W @Rm+,@Rn+
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA mm mm
IF — — ID EX ⋅ ⋅ ⋅
IF — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after seven stages: IF, ID, EX, MA, MA, mm, mm. mm indicates a state in
which the multiplier is operating.
See section 8.7, Contention Due to Multiplier, for general pipeline details. This instruction has
three execution slots, a latency of five, and four lock states. Detailed examples where there are
consecutive instructions relating to the pipeline of this instruction or the multiplier are given
below.
(a) When a MAC.W instruction is immediately followed by a MAC.W or MAC.L instruction
There is no multiplier contention.
MAC.W @Rm+,@Rn+
MAC.W @Rm+,@Rn+
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA mm mm
IF — — ID EX MA MA mm mm
IF — — — ID EX ⋅ ⋅ ⋅
(b) When a MAC.W instruction is immediately followed by a MULS.W, MULU.W, DMULS.W,
DMULU.W, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the MAC.W instruction locks the multiplier, stalling occurs a further 2-slot interval back.
Rev. 3.00 Jul 08, 2005 page 392 of 484
REJ09B0051-0300