SH-2A Datasheet, PDF (204/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Example 1:
SHLL16
TST
BT
CMP/HS
BT
DIV0U
.arepeat
DIV1
.aendr
ROTCL
EXTU.W
R0
R0,R0
ZERO_DIV
R0,R1
OVER_DIV
16
R0,R1
R1
R1,R1
; R1 (32 bits) / R0 (16 bits) = R1 (16 bits):Unsigned
; Upper 16 bits = divisor, lower 16 bits = 0
; Zero division check
;
; Overflow check
;
; Flag initialization
;
; Repeat 16 times
;
;
; R1 = Quotient
Example 2:
TST
BT ZERO_DIV
CMP/HS
BT OVER_DIV
DIV0U
.arepeat
ROTCL
DIV1
.aendr
ROTCL
; R1:R2 (64 bits)/R0 (32 bits) = R2 (32 bits):Unsigned
R0,R0
; Zero division check
;
;R0,R1 ; Overflow check
;
; Flag initialization
32
;
R2
; Repeat 32 times
R0,R1
;
;
R2
; R2 = Quotient
Rev. 3.00 Jul 08, 2005 page 190 of 484
REJ09B0051-0300