SH-2A Datasheet, PDF (359/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.3.2 Details of Contention Due to Wait for Result of Previously Issued Instruction
When the result of a previously issued instruction is used as a source, execution is performed after
a wait equivalent to the latency of that instruction. Cases where this applies include the following:
• When waiting for the result of a memory access (see section 8.5, Effect of Memory Load
Instruction on Pipeline, for details)
• When waiting for the result of an FPU operation (see section 8.6, Contention Due to FPU, for
details)
• When waiting for the result of multiplication (see section 8.7, Contention Due to Multiplier,
for details)
If the preceding instruction causes contention in these cases, the succeeding instruction must wait
to be executed.
If the succeeding instruction causes contention, the preceding instruction is executed if there is no
other contention.
8.3.3 Details of Register Contention and Flag Contention
In the following cases, register contention or flag contention occurs in the same slot.
(1) When the succeeding instruction uses the destination register or flag of the preceding
instruction as a source register or flag (excluding a case where the preceding instruction is a
zero-latency instruction) (figures 8.18 and 8.19)
CMP/EQ R2,R3
BF
IF ID EX
IF — ID EX
Figure 8.18 Example of Flag Contention between Preceding Destination
and Succeeding Source
MOV R3,R4
ADD R4,R5
IF ID EX
IF ID EX
Figure 8.19 Example of No Contention between Zero-Latency Instruction and Succeeding
Instruction
Rev. 3.00 Jul 08, 2005 page 345 of 484
REJ09B0051-0300