SH-2A Datasheet, PDF (34/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
Table 3.4 Exception Vector Table Address Calculation
Exception Source
Vector Table Address Calculation
Reset
Vector table address = (vector table address offset)
= (vector number) × 4
Address error, RAM error,
register bank error, interrupt,
instruction
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Note: VBR: Vector base register
Vector table address offset: See table 3.3.
Vector number: See table 3.3.
3.2 Resets
3.2.1 Types of Reset
A reset is the highest-priority exception handling source. There are two types of reset: a power-on
reset and a manual reset. The CPU state is initialized by both a power-on reset and a manual reset.
The FPU state is initialized by a power-on reset, but not by a manual reset. Refer to the hardware
manual of the relevant product for information on the states of on-chip peripheral modules, the
PFC, and I/O ports.
3.2.2 Power-On Reset
When a power-on reset condition is detected, the chip enters the power-on reset state. See
“Power-On Reset” in the Exception Handling section of the hardware manual for the relevant
product for details of power-on reset conditions.
When the power-on reset state is released, power-on reset exception handling is started. CPU
operations are as follows.
1. The initial value of the program counter (PC) (i.e. the execution start address) is fetched from
the exception vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask bits (I3 to I0) in
the status register (SR) are set to (H'F) (1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of INTC is also initialized to 0. In addition, in products with an FPU, FPSCR
is initialized to H'00040001.
Rev. 3.00 Jul 08, 2005 page 20 of 484
REJ09B0051-0300