SH-2A Datasheet, PDF (476/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Operation
• Single-Precision
The CPU pipeline ends after four stages – IF, ID, EX, MA – and the FPU pipeline after four
stages – IF, DF, EX, NA.
• Double-Precision
The CPU pipeline ends after five stages – IF, ID, EX, MA, MA – and the FPU pipeline after
five stages – IF, DF, EX, EX, NA.
Instruction Issuance
These instructions use the FPU load/store pipeline and memory access pipeline.
Parallel Execution Capability
FMOV.D instruction is a multi-cycle instruction, and cannot be executed in parallel with a
subsequent instruction. (See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 462 of 484
REJ09B0051-0300