SH-2A Datasheet, PDF (11/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.41 NOP ........... No OPeration ............................... System Control Instruction...... 236
6.4.42 NOT ........... NOT-logical complement ............ Logical Instruction................... 237
6.4.43 OR .............. OR logical .................................. Logical Instruction................... 238
6.4.44 ROTCL ...... ROTate with Carry Left .............. Shift Instruction ....................... 240
6.4.45 ROTCR ...... ROTate with Carry Right ............ Shift Instruction ....................... 241
6.4.46 ROTL ......... ROTate Left ................................ Shift Instruction ....................... 242
6.4.47 ROTR ........ ROTate Right .............................. Shift Instruction ....................... 243
6.4.48 RTE ............ ReTurn from Exception ............... System Control Instruction...... 244
6.4.49 RTS ............ ReTurn from Subroutine ............. Branch Instruction ................... 246
6.4.50 SETT .......... SET T bit ..................................... System Control Instruction...... 248
6.4.51 SHAL ......... SHift Arithmetic Left .................. Shift Instruction ....................... 249
6.4.52 SHAR ........ SHift Arithmetic Right ................ Shift Instruction ....................... 250
6.4.53 SHLL ......... SHift Logical Left ....................... Shift Instruction ....................... 251
6.4.54 SHLLn ....... n bits SHift Logical Left .............. Shift Instruction ....................... 252
6.4.55 SHLR ......... SHift Logical Right ..................... Shift Instruction ....................... 254
6.4.56 SHLRn ....... n bits SHift Logical Right ........... Shift Instruction ....................... 255
6.4.57 SLEEP ....... SLEEP ......................................... System Control Instruction...... 257
6.4.58 STC ............ STore Control register ................. System Control Instruction...... 258
6.4.59 STS ............ STore System register ................. System Control Instruction...... 260
6.4.60 SUB ........... SUBtract binary ........................... Arithmetic Instruction ............. 262
6.4.61 SUBC ......... SUBtract with Carry .................... Arithmetic Instruction ............. 263
6.4.62 SUBV ........ SUBtract with (V flag) underflow check
...................................................... Arithmetic Instruction ............. 264
6.4.63 SWAP ........ SWAP register halves .................. Data Transfer Instruction......... 266
6.4.64 TAS ............ Test And Set ................................ Logical Instruction................... 268
6.4.65 TRAPA ...... TRAP Always ............................. System Control Instruction...... 269
6.4.66 TST ............ TeST logical ................................ Logical Instruction................... 271
6.4.67 XOR ........... eXclusive OR logical .................. Logical Instruction................... 273
6.4.68 XTRCT ...... eXTRaCT .................................... Data Transfer Instruction......... 275
6.5 Floating-Point Instructions and FPU-Related CPU Instructions....................................... 276
6.5.1 FABS ......... Floating-point ABSolute value .... Floating-Point Instruction........ 276
6.5.2 FADD ........ Floating-point ADD .................... Floating-Point Instruction........ 277
6.5.3 FCMP ........ Floating-point CoMPare .............. Floating-Point Instruction........ 280
6.5.4 FCNVDS ... Floating-point CoNVert Double to Single precision
...................................................... Floating-Point Instruction........ 284
6.5.5 FCNVSD ... Floating-point CoNVert Single to Double precision
...................................................... Floating-Point Instruction........ 287
6.5.6 FDIV .......... Floating-point DIVide ................. Floating-Point Instruction........ 289
6.5.7 FLDI0 ........ Floating-point LoaD Immediate 0.0
...................................................... Floating-Point Instruction........ 293
Rev. 3.00 Jul 08, 2005 page xi of xiv