SH-2A Datasheet, PDF (448/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When an STS instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the STS instruction does not lock the multiplier, parallel execution is performed.
STS MACH,Rn
MUL.L Rm,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm WB
IF ID mm mm mm
IF ID EX ⋅ ⋅ ⋅
(c) When an STS instruction is immediately followed by a STS (register) or STS.L (memory)
instruction.
Parallel execution is not possible, as contention occurs with the multiplication result read bus.
STS MACH,Rn
STS MACL,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
IF — ID EX WB
IF ID EX ⋅ ⋅ ⋅
(d) When an STS instruction is immediately followed by an LDS.L (memory) instruction
Parallel execution is performed.
There is no multiplier contention.
STS MACH,Rn
LDS.L @Rn+,MACL
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX WB
IF ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
Instruction Issuance
These instructions use the multiplier, but do not lock it.
These instructions use the multiplication result read path.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 434 of 484
REJ09B0051-0300