SH-2A Datasheet, PDF (77/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
5.1.5 Branch Instructions
Table 5.7 Branch Instructions
Compatibility
Instruction
BF label
BF/S label
Code
Operation
10001011dddddddd When T = 0, disp × 2 + PC → PC,
when T = 1, nop
10001111dddddddd Delayed branch, when T = 0, disp
× 2 + PC → PC, when T = 1, nop
Cycles
3/1^*
T Bit
―
SH2E
SH4
New
SH-2A/
SH2A-
FPU
Yes Yes
2/1^*
― Yes Yes
BT label
BT/S label
BRA label
10001001dddddddd When T = 1, disp × 2 + PC → PC, 3/1^*
when T = 0, nop
10001101dddddddd Delayed branch, when T = 1, disp 2/1^*
× 2 + PC → PC, when T = 0, nop
1010dddddddddddd Delayed branch, disp × 2 + PC →
2
PC
― Yes Yes
― Yes Yes
― Yes Yes
BRAF Rm
0000mmmm00100011 Delayed branch, Rm + PC → PC
2
BSR label
1011dddddddddddd Delayed branch, PC → PR, disp ×
2
2 + PC → PC
BSRF Rm
0000mmmm00000011 Delayed branch, PC → PR, Rm +
2
PC → PC
JMP @Rm
0100mmmm00101011 Delayed branch, Rm → PC
2
JSR @Rm
0100mmmm00001011 Delayed branch, PC → PR,
2
Rm → PC
JSR/N @Rm
0100mmmm01001011 PC - 2 → PR, Rm → PC
3
JSR/N @@(disp8, TBR) 10000011dddddddd PC - 2 → PR, (disp×4+TBR) → PC 5
RTS
0000000000001011 Delayed branch, PR → PC
2
RTS/N
0000000001101011 PR → PC
3
RTV/N Rm
0000mmmm01111011 Rm → R0, PR → PC
3
Note: * One state when the program does not branh.
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
― Yes Yes
―
Yes
―
Yes
― Yes Yes
―
Yes
―
Yes
Rev. 3.00 Jul 08, 2005 page 63 of 484
REJ09B0051-0300