SH-2A Datasheet, PDF (420/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) Memory Logical Operation Instructions
Instruction Type
TST.B #imm,@(R0,GBR)
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA EX
IF — — ID EX ⋅ ⋅ ⋅
IF — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after five stages: IF, ID, EX, MA, EX.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 406 of 484
REJ09B0051-0300