SH-2A Datasheet, PDF (29/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
Section 3 Exception Handling
3.1 Overview
3.1.1 Exception Handling Types and Priority
As table 3.1 indicates, exception handling may be caused by a reset, address error, RAM error,
register bank error, interrupt, or instruction. Exception handling is prioritized as shown in table
3.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of
priority.
Rev. 3.00 Jul 08, 2005 page 15 of 484
REJ09B0051-0300