SH-2A Datasheet, PDF (180/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Operation
BFS(long d) /* BFS disp */
{
long disp;
unsigned long temp;
temp=PC;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
if (T==0) {
PC=PC+(disp<<1);
Delay_Slot(temp+2);
}
else PC+=2;
}
Example:
CLRT
BT/S TRGET_T
NOP
BF/S TRGET_F
ADD R0,R1
NOP
..........
TRGET_F:
; T is always 0
; Does not branch, because T = 0
;
; Branches to TRGET_F, because T = 0
; Executed before branch.
; ← The PC location is used to calculate the branch destination
address of the BF/S instruction
; ← Branch destination of the BF/S instruction
Note:
When a delayed branch instruction is used, the branching operation takes place after the
slot instruction is executed, but the execution of instructions (register update, etc.) takes
place in the sequence delayed branch instruction → delayed slot instruction. For example,
even if a delayed slot instruction is used to change the register where the branch
destination address is stored, the register content previous to the change will be used as the
branch destination address.
Rev. 3.00 Jul 08, 2005 page 166 of 484
REJ09B0051-0300