SH-2A Datasheet, PDF (402/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(9) Memory Store Instructions (MOVMU.L, MOVML.L)
Instruction Types
MOVMU.L Rm,@-R15
MOVML.L Rm,@-R15
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA ⋅ ⋅ ⋅ MA MA MA
IF — — — ⋅ ⋅ ⋅ ID EX ⋅ ⋅ ⋅
IF — — ⋅ ⋅ ⋅ — ID EX ⋅ ⋅ ⋅
Operation
These instructions perform saving to the stack. The pipeline is in the form IF, ID, EX, MA, MA,
MA, ... MA, with MA repeated as often as necessary. There is no WB stage as there is no return
of data to the register.
Instruction Issuance
If there is an uncompleted instruction in the pipeline when these instructions are decoded,
execution of these instructions will be delayed.
These instructions use the memory access pipeline.
Parallel Execution Capability
These are multi-cycle instructions, and cannot be executed in parallel with a subsequent
instruction.
Rev. 3.00 Jul 08, 2005 page 388 of 484
REJ09B0051-0300