SH-2A Datasheet, PDF (457/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.9.7 Exception Handling
(1) Interrupt Exception Handling
Instruction Type
Interrupt exception handling
Pipeline
• No banking
Interrupt
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX MA MA MA
IF ⋅ ⋅ ⋅
IF ⋅ ⋅ ⋅
IF ID
• Banking, no overflow
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
Interrupt
IF ID EX EX MA MA MA MA
Next instruction
IF ⋅ ⋅ ⋅
Branch destination
IF ID
• Banking and overflow
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
Interrupt
IF ID EX EX MA MA MA ⋅ ⋅ ⋅ MA
Next instruction
IF ⋅ ⋅ ⋅
Branch destination
IF
⋅ ⋅ ⋅ ID
Operation
An interrupt is accepted in the ID stage of an instruction, and processing from that ID stage
onward is replaced by an exception handling sequence.
Interrupt handling operations are different when there is no banking, when there is banking, and
when there is banking and overflow.
When there is no banking, the pipeline ends after seven stages: IF, ID, EX, EX, MA, MA, MA.
Rev. 3.00 Jul 08, 2005 page 443 of 484
REJ09B0051-0300