SH-2A Datasheet, PDF (35/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
4. The values fetched from the exception vector table are set in the program counter (PC) and
stack pointer (SP), and program execution is started.
Power-on reset processing must always be executed when the system is powered on.
3.2.3 Manual Reset
When a manual reset condition is detected, the chip enters the manual reset state. See “Manual
Reset” in the Exception Handling section of the hardware manual for the relevant product for
details of manual reset conditions.
When the manual reset state is released, manual reset exception handling is started. CPU
operations are as follows.
1. The initial value of the program counter (PC) (i.e. the execution start address) is fetched from
the exception vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask bits (I3 to I0) in
the status register (SR) are set to (H'F) (1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of INTC is also initialized to 0.
4. The values fetched from the exception vector table are set in the program counter (PC) and
stack pointer (SP), and program execution is started.
When a manual reset occurs, the bus cycle is held. If a manual reset occurs while the bus is
released or during a DMAC burst transfer, manual reset exception handling is held pending until
the CPU acquires the bus. However, if the interval from occurrence of a manual reset until the end
of a bus cycle exceeds a given number of cycles, the internal manual reset source is not held
pending but is ignored, and manual reset exception handling is not performed. See “Manual
Reset” in the Exception Handling section of the hardware manual for the relevant product for
details.
A manual reset initializes the CPU and the BN bit in IBNR of the INTC. The FPU and other
modules are not initialized.
Rev. 3.00 Jul 08, 2005 page 21 of 484
REJ09B0051-0300