SH-2A Datasheet, PDF (479/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(14) Floating-Point Operation Instructions (Excluding FDIV, FSQRT, FLOAT, and FTRC)
Instruction Types
FADD
FMAC
FMUL
FSUB
FADD
FMUL
FSUB
FRm,FRn
FR0,FRm,FRn
FRm,FRn
FRm,FRn
DRm,DRn
DRm,DRn
DRm,DRn
Pipeline
• Single-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
: CPU pipeline
IF DF E1 E2 SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF EX NA SF : FPU pipeline
• Double-Precision
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
: CPU pipeline
IF DF E1 E1 E1 E1 E1 E1 E2 SF : FPU pipeline
IF ID EX MA WB
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
Rev. 3.00 Jul 08, 2005 page 465 of 484
REJ09B0051-0300