SH-2A Datasheet, PDF (468/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(7) Some floating-point register-register transfer instructions, floating-point register-
immediate instructions, and floating-point operation instructions
Instruction Types
FLDS
FMOV
FSTS
FLDI0
FLDI1
FABS
FNEG
FABS
FNEG
FRm,FPUL
FRm,FRn
FPUL,FRn
FRn
FRn
FRn
FRn
DRn
DRn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
: CPU pipeline
IF DF EX NA SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF E1 E2 SF
: FPU pipeline
IF ID EX ⋅ ⋅ ⋅
: CPU pipeline
IF DF E1 E2 E3 : FPU pipeline
Operation
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after five stages –
IF, DF, EX, NA, SF. Contention does not occur even if one of these instructions is immediately
followed by an instruction that reads the destination of that instruction.
Instruction Issuance
These instructions use the FPU load/store pipeline.
Parallel Execution Capability
These are zero-latency instructions. Parallel execution is possible even if one of these instructions
is executed as a preceding instruction and the succeeding instruction uses FRn, FPUL.
Rev. 3.00 Jul 08, 2005 page 454 of 484
REJ09B0051-0300