SH-2A Datasheet, PDF (147/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.23 MOVML.L
MOVe Multi-register Lower part
R0-Rn Register Save/Restore Instruction
Data Transfer Instruction
SH-2A/SH2A-FPU (New)
Format
MOVML.L Rm, @-R15
MOVML.L @R15+, Rn
Abstract
Code
R15 - 4 → R15, Rm → (R15)
R15 - 4 → R15, Rm - 1 → (R15)
:
R15 - 4 → R15, R0 → (R15)
0100mmmm11110001
Note: When Rm = R15, read Rm
as PR
(R15) → R0, R15 + 4 → R15
(R15) → R1, R15 + 4 → R15
:
(R15) → Rn, R15 + 4 → R15
0100nnnn11110101
Note: When Rn = R15, read Rn as
PR
Cycle T Bit
1 to 16 ―
1 to 16 ―
Description
Transfers a source operand to a destination. This instruction performs transfer between a number
of general registers (R0 to Rn/Rm) not exceeding the specified register number and memory with
the contents of R15 as its address.
If R15 is specified, PR is transferred instead of R15. That is, when nnnn(mmmm) = 1111 is
specified, R0 to R14 and PR are the general registers subject to transfer.
Operation
MOVLMML (long m) /*MOVML.L Rm, @-R15*/
{
long i;
for (i=m; i≥0; i--)
{
if (i==15)
{
Write_Long (R[15]-4, PR);
R[15]-=4;
}
else
Rev. 3.00 Jul 08, 2005 page 133 of 484
REJ09B0051-0300