SH-2A Datasheet, PDF (263/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.51
SHAL
One-Bit Left
Arithmetic Shift
SHift Arithmetic Left
Section 6 Instruction Descriptions
Shift Instruction
Format
SHAL Rn
Abstract
T ← Rn ← 0
Code
0100nnnn00100000
Cycle
1
T Bit
MSB
Description
Arithmetically shifts the contents of general register Rn to the left by one bit, and stores the result
in Rn. The bit that is shifted out of the operand is transferred to the T bit (figure 6.7).
SHAL
MSB
T
LSB
0
Figure 6.7 Shift Arithmetic Left
Operation
SHAL(long n) /* SHAL Rn (Same as SHLL) */
{
if ((R[n]&0x80000000)==0) T=0;
else T=1;
R[n]<<=1;
PC+=2;
}
Example:
SHAL R0
; Before execution: R0 = H'80000001, T = 0
; After execution: R0 = H'00000002, T = 1
Rev. 3.00 Jul 08, 2005 page 249 of 484
REJ09B0051-0300