SH-2A Datasheet, PDF (272/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.58 STC
STore Control register
Store from Control Register
System Control Instruction
Format
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@-Rn
STC.L GBR,@-Rn
STC.L VBR,@-Rn
Abstract
SR → Rn
GBR → Rn
VBR → Rn
Rn – 4 → Rn, SR → (Rn)
Rn – 4 → Rn, GBR → (Rn)
Rn – 4 → Rn, VBR → (Rn)
Code
Cycle
0000nnnn00000010 2
0000nnnn00010010 1
0000nnnn00100010 1
0100nnnn00000011 2
0100nnnn00010011 1
0100nnnn00100011 1
T Bit
—
—
—
—
—
—
Description
Stores control register SR, GBR, or VBR data into a specified destination.
Operation
STCSR(long n) /* STC SR,Rn */
{
R[n]=SR;
PC+=2;
}
STCGBR(long n) /* STC GBR,Rn */
{
R[n]=GBR;
PC+=2;
}
STCVBR(long n) /* STC VBR,Rn */
{
R[n]=VBR;
PC+=2;
}
STCMSR(long n) /* STC.L SR,@-Rn */
{
R[n]-=4;
Write_Long(R[n],SR);
Rev. 3.00 Jul 08, 2005 page 258 of 484
REJ09B0051-0300