SH-2A Datasheet, PDF (135/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.3.17 LDBANK
LoaD register BANK
Transfer to Specified Register Bank Entry
Section 6 Instruction Descriptions
System Control Instruction
SH-2A/SH2A-FPU (New)
Format
LDBANK @Rm, R0
Abstract
(Specified register bank entry) → R0
Code
0100mmmm11100101
Cycle
6
T Bit
―
Description
The register bank entry indicated by the contents of general register Rm is transferred to general
register R0. The register bank number and register stored in the bank are specified by general
register Rm.
31
16 15
(Rm) 0 ................................... 0
BN
76
210
EN 00
BN: Bank number field
EN: Entry number field
BN
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001000
000001001
000001010
000001011
000001100
000001101
000001110
Register Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
EN
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Entry in Register Bank
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
MACH
Interrupt vector offset
PR
GBR
MACL
Rev. 3.00 Jul 08, 2005 page 121 of 484
REJ09B0051-0300