SH-2A Datasheet, PDF (19/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
2.2.2 Control Registers
There are four control registers, each 32 bits in length: the status register (SR), global base register
(GBR), vector base register (VBR), and jump table base register (TBR).
The status register indicates the processing status of instructions.
The global base register is used as the base address in the GBR indirect addressing mode and to
transfer register data from on-chip peripheral modules.
The vector base register is used as the base address for the exception processing vector area,
including interrupts.
The table base register is used as the base address for the function table area.
(1) Status Register, SR
(32-bit, initial value = 0000 0000 0000 0000 00X0 00XX 1111 00XX) (X = undefined))
31
15 14 13 12 10 9 8 7
43210
—
BO CS —
MQ
IMASK
— ST
Note: —: Reserved bits. Always read as 0. The write value should always be 0.
BO: Indicates that a register bank has overflowed.
CS: Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-
limit value or fallen below the saturation lower-limit value.
M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.
IMASK: Interrupt mask level
S: Specifies a saturation operation for a MAC instruction.
T: True/false condition or carry/borrow bit
(2) Global Base Register, GBR (32-bit, initial value = undefined)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3) Vector Base Register, VBR (32-bit, initial value = H'0000 0000)
VBR is referenced as the branch destination base address in the event of an exception or interrupt.
Rev. 3.00 Jul 08, 2005 page 5 of 484
REJ09B0051-0300