SH-2A Datasheet, PDF (442/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(7) STC.L Instruction
Instruction Type
STC.L SR, @-Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX MA
IF — ID EX ⋅ ⋅ ⋅
IF — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after five stages: IF, ID, EX, EX, MA.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Although this instruction uses the memory access pipeline, parallel execution is possible if the
preceding instruction is a single-cycle memory access instruction.
Rev. 3.00 Jul 08, 2005 page 428 of 484
REJ09B0051-0300