SH-2A Datasheet, PDF (294/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5.3
FCMP
Floating-Point
Comparison
Floating-point CoMPare
Floating-Point Instruction
No. PR Format
Abstract
1. 0 FCMP/EQ FRm,FRn (FRn==FRm)?1:0 → T
2. 1 FCMP/EQ DRm,DRn (DRn==DRm)?1:0 → T
3. 0 FCMP/GT FRm,FRn (FRn>FRm)?1:0 → T
4. 1 FCMP/GT DRm,DRn (DRn>DRm)?1:0 → T
Code
Cycle
1111nnnnmmmm0100 1
1111nnn0mmm00100 2
1111nnnnmmmm0101 1
1111nnn0mmm00101 2
T Bit
1/0
1/0
1/0
1/0
Description
1. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
numbers in FRn and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
2. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
3. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
numbers in FRn and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise.
4. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.
Operation
void FCMP_EQ(int m,n) /* FCMP/EQ FRm,FRn */
{
pc += 2;
clear_cause();
if(fcmp_chk (m,n) == INVALID) fcmp_invalid();
else if(fcmp_chk (m,n) == EQ) T = 1;
else
T = 0;
}
void FCMP_GT(int m,n) /* FCMP/GT FRm,FRn */
{
pc += 2;
clear_cause();
if ((fcmp_chk (m,n) == INVALID) ||
(fcmp_chk (m,n) == UO)) fcmp_invalid();
Rev. 3.00 Jul 08, 2005 page 280 of 484
REJ09B0051-0300