SH-2A Datasheet, PDF (347/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 Register Banks
7.6 SR Register Bank Overflow Bit (BO Bit)
The BO bit is modified when the contents of the SR register are retrieved by the RTE instruction.
The BO bit is not modified when a RESBANK instruction is executed. The BO bit is set to 1 if
exception generation by the interrupt controller is not enabled in cases where a bank overflow
occurs during an interrupt. If exception generation by the interrupt controller is enabled for cases
when a bank overflow occurs during an interrupt, the BO bit is not modified. The BO bit is
modified by the LDC Rm.SR and LDC.L @Rmt.SR instructions.
Rev. 3.00 Jul 08, 2005 page 333 of 484
REJ09B0051-0300