SH-2A Datasheet, PDF (410/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(4) Multiply Instructions
Instruction Types
MULS.W Rm,Rn
MULU.W Rm,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after four stages: IF, ID, mm, mm. mm indicates a state in which the multiplier
is operating.
See section 8.7, Contention Due to Multiplier, for general pipeline details. These instructions
have one execution slot, a latency of two, and one lock state. Detailed examples where there are
consecutive instructions relating to the pipeline of this instruction or the multiplier are given
below.
(a) When a MULS.W instruction is immediately followed by a MAC.W or MAC.L instruction
There is no multiplier contention.
MULS.W
MAC.W
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm
IF ID EX MA MA mm mm
IF — ID EX ⋅ ⋅ ⋅
Rev. 3.00 Jul 08, 2005 page 396 of 484
REJ09B0051-0300