SH-2A Datasheet, PDF (423/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(6) Memory-Tbit Logical Operation Instructions
Instruction Types
BAND.B
BANDNOT.B
BLD.B
BLDNOT.B
BOR.B
BORNOT.B
BXOR.B
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA EX
IF — ID EX ⋅ ⋅ ⋅
IF — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after five stages: IF, ID, EX, MA, EX.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
These are 32-bit instructions, and cannot be used in parallel execution. If the instruction following
this instruction is BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, or
BXOR, the final step is executed in parallel with the instruction that follows. Parallel execution
with the final step is not possible with any other instruction. (See section 8.3.5, Details of
Contention Due to 32-Bit Instruction).
Rev. 3.00 Jul 08, 2005 page 409 of 484
REJ09B0051-0300