SH-2A Datasheet, PDF (309/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.5.9
FLDS
Transfer to System
Register
Floating-point
LoaD to System register
Section 6 Instruction Descriptions
Floating-Point Instruction
Format
FLDS FRm,FPUL
Abstract
FRm → FPUL
Code
Cycle
1111mmmm00011101 1
T Bit
—
Description
This instruction loads the contents of floating-point register FRm into system register FPUL.
Operation
void FLDS(int m, float *FPUL)
{
*FPUL = FR[m];
pc += 2;
}
Possible Exceptions:
None
Rev. 3.00 Jul 08, 2005 page 295 of 484
REJ09B0051-0300