SH-2A Datasheet, PDF (37/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.3.2 Address Error Exception Handling
When an address error occurs, address error exception handling is started after the end of the bus
cycle in which the address error occurred and completion of the currently executing instruction.
CPU operations are as follows.
1. The start address of the exception service routine corresponding to the address error is fetched
from the exception handling vector table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
instruction following the last instruction executed.
4. Execution jumps to the address fetched from the exception handling vector table and program
execution commences. The jump is not a delayed branch.
3.4 RAM Errors
3.4.1 RAM Error Sources
A RAM error occurs in the event of a software error in an on-chip RAM read access. For details,
see “RAM Errors” in the Exception Handling section of the hardware manual for the relevant
product.
3.4.2 RAM Error Exception Handling
When a RAM error occurs, RAM error exception handling is started after the end of the bus cycle
in which the error occurred and completion of the currently executing instruction. CPU operations
are as follows.
1. The start address of the exception service routine corresponding to the RAM error is fetched
from the exception handling vector table.
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
instruction following the last instruction executed.
4. Execution jumps to the address fetched from the exception handling vector table and program
execution commences. The jump is not a delayed branch.
Rev. 3.00 Jul 08, 2005 page 23 of 484
REJ09B0051-0300