SH-2A Datasheet, PDF (421/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(4) TAS Instruction
Instruction Type
TAS.B @Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA EX MA
IF — — ID EX ⋅ ⋅ ⋅
IF — — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after six stages: IF, ID, EX, MA, EX, MA.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 407 of 484
REJ09B0051-0300