SH-2A Datasheet, PDF (282/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.64
TAS
Memory Test
and Bit Setting
Test And Set
Logical Instruction
Format
TAS.B @Rn
Abstract
Code
Cycle
When (Rn) is 0, 1 → T, 1 → MSB 0100nnnn00011011 3
of (Rn)
T Bit
Test results
Description
Reads byte data from the address specified by general register Rn, and sets the T bit to 1 if the data
is 0, or clears the T bit to 0 if the data is not 0. Then, data bit 7 is set to 1, and the data is written to
the address specified by Rn. During this operation, the bus is not released.
Operation
TAS(long n) /* TAS.B @Rn */
{
long temp;
temp=(long)Read_Byte(R[n]);
if (temp==0) T=1;
else T=0;
temp|=0x00000080;
Write_Byte(R[n],temp);
PC+=2;
}
/* Bus Lock enable */
/* Bus Lock disable */
Example:
_LOOP TAS.B @R7
BF
_LOOP
; R7 = 1000
; Loops until data in address 1000 is 0
Rev. 3.00 Jul 08, 2005 page 268 of 484
REJ09B0051-0300