SH-2A Datasheet, PDF (358/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
STS MACH,R0
STS FPUL,R1
IF ID EX MA WB
IF — ID mm mm mm WB
Note: The two instructions using the multiplication result read bus conflict with each other.
Figure 8.14 Example of Contention between Instructions Using Multiplication Result
Read Bus
(3) When the preceding instruction and succeeding instruction are both shift instructions or rotate
instructions (figure 8.15)
SHAD R0,R1
SHAD R2,R3
IF ID EX
IF — ID EX
Figure 8.15 Example of Shift Instruction Contention
(4) When the preceding instruction and succeeding instruction are both FPU arithmetic operation
instructions (figure 8.16)
With regard to FPU arithmetic operation instructions, complex resource contention occurs with
double-precision instructions or with FDIV or FSQRT instructions. See section 8.6,
Contention Due to FPU, for details.
FADD FR0,FR1
FADD FR2,FR3
IF DF E1 E2 SF
IF — DF E1 E2 SF
Figure 8.16 Example of FPU Arithmetic Operation Instruction Contention
(5) When the preceding instruction and succeeding instruction are both FPU load/store
instructions (figure 8.17)
FNEG FR0
FMOV FR1,FR3
IF DF EX NA SF
IF — DF EX NA SF
Figure 8.17 Example of FPU Load/Store Instruction Contention
Rev. 3.00 Jul 08, 2005 page 344 of 484
REJ09B0051-0300