SH-2A Datasheet, PDF (86/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
(2) Structure Access Instructions
MOV.B/W/L Rm, @(disp12, Rn), MOV.B/W/L @(disp12, Rm), Rn
MOVU.B/W @(disp12, Rm), Rn
FMOV.S FRm, @(disp12, Rn), FMOV.S @(disp12, Rm), FRn
FMOV.D DRm, @(disp12, Rn), FMOV.D @(disp12, Rm), DRn
These instructions reference memory by specifying a 12-bit displacement located in the instruction
code. An MOVU unsigned load instruction that automatically performs execution of zero
extension has also been added.
(3) Bit Manipulation Instructions (Operating on Memory)
BAND.B #imm3, @(disp12, Rn), BOR.B #imm3, @(disp12, Rn)
BCLR.B #imm3, @(disp12, Rn), BSET.B #imm3, @(disp12, Rn)
BST.B #imm3, @(disp12, Rn), BLD.B #imm3, @(disp12, Rn)
BXOR.B #imm3, @(disp12, Rn)
BANDNOT.B #imm3, @(disp12, Rn), BORNOT.B #imm3, @(disp12, Rn)
BLDNOT.B #imm3, @(disp12, Rn)
The BAND.B, BOR.B, and BXOR.B instructions perform logical operations between a bit in
memory and the T bit, and store the result in the T bit. The BCLR.B and BSET.B instructions
manipulate a bit in memory. The BST.B and BLD.B instructions execute a transfer between a bit
in memory and the T bit. The BANDNOT.B and BORNOT.B instructions perform logical
operations between the value resulting from inverting a bit in memory and the T bit, and store the
result in the T bit. The BLDNOT.B instruction inverts a bit in memory and stores the result in the
T bit. Bits other than the specified bit are not affected.
(4) Bit Manipulation Instructions (Operating on a General Register)
BCLR #imm3, Rn, BSET #imm3, Rn
BST #imm3, Rn , BLD #imm3, Rn
The BCLR and BSET instructions manipulate one of the LSB 8 bits of a general register Rn. The
BST and BLD instructions execute a transfer between one of the LSB 8 bits of a general register
Rn and the T bit. Bits other than the specified bit are not affected.
Rev. 3.00 Jul 08, 2005 page 72 of 484
REJ09B0051-0300