SH-2A Datasheet, PDF (438/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) System Control ALU Instruction
Instruction Type
STC SR,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX EX
IF — ID EX ⋅ ⋅ ⋅
IF — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after four stages: IF, ID, EX, EX. In the second EX stage, the data operation is
completed via the ALU.
Instruction Issuance
No particular comments
A typical pipeline when performing a CS bit read is shown below.
CLIP
STC
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF — ID EX EX
IF — ID EX ⋅ ⋅ ⋅
IF — ID EX ⋅ ⋅ ⋅
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 424 of 484
REJ09B0051-0300