SH-2A Datasheet, PDF (494/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Appendix A SH-2A/SH2A-FPU Parallel Execution
Classifi- Classifi-
cation of cation of
First
Second
Instruction Instruction
MW
MR
AND.B
BST.B
TAS.B
MW
MW
MOV.B
MOV.B
MOV.B
MOV.W
MOV.W
MOV.L
MOV.L
MOVML.L
STC.L
ML
ML
STS
MU
MU
CLRMAC
MUL.L
LDS
ML,MU
ML
MULR
SF
SF
DIVU
EXTU.B
ROTCR
SHAD
SHLD
SHLL2
SHLR16
SWAP.B
FL
FL
FABS
FLDI1
FMOV
FSTS
ML,FL
ML,FL
STS
FP
FP
FADD
FCMP/GT
FDIV
FLOAT
FMUL
FSQRT
FTRC
Instruction
#imm,@(R0,GBR) BCLR.B
#imm3,@(disp12,Rn) OR.B
@Rn
XOR.B
R0,@(disp,GBR)
MOV.B
Rm,@Rn
MOV.B
Rm,@(disp12,Rn) MOV.W
Rm,@(R0,Rn)
MOV.W
R0,@Rn+
MOV.W
Rm,@(disp,Rn)
MOV.L
Rm,@-Rn
MOV.L
Rm,@-R15
MOVMU.L
VBR,@-Rn
STS.L
MACH,Rn
STS
DMULS.L
Rm,Rn
MULS.W
Rm,MACL
LDS
R0,Rn
R0,Rn
EXTS.B
Rm,Rn
EXTU.W
Rn
ROTL
Rm,Rn
SHAL
Rm,Rn
SHLL
Rn
SHLL8
Rn
SHLR2
Rm,Rn
SWAP.W
DRn
FABS
FRn
FLDS
FRm,FRn
FNEG
FPUL,FRn
FPUL,Rn
DRm,DRn
FADD
FRm,FRn
FCNVDS
DRm,DRn
FDIV
FPUL,FRn
FMAC
FRm,FRn
FSCHG
FRn
FSUB
DRm,FPUL
FTRC
#imm3,@(disp12,Rn) BSET.B
#imm,@(R0,GBR) STC.L
#imm,@(R0,GBR)
R0,@(disp,Rn)
MOV.B
Rm,@-Rn
MOV.B
R0,@(disp,GBR)
MOV.W
Rm,@Rn
MOV.W
Rm,@(disp12,Rn) MOV.L
Rm,@(R0,Rn)
MOV.L
R0,@Rn+
MOV.L
Rm,@-R15
STC.L
PR,@-Rn
MACL,Rn
Rm,Rn
DMULU.L
Rm,Rn
MULU.W
Rm,MACH
Rm,Rn
Rm,Rn
Rn
Rn
Rn
Rn
Rn
Rm,Rn
FRn
FRm,FPUL
DRn
EXTS.W
ROTCL
ROTR
SHAR
SHLL16
SHLR
SHLR8
XTRCT
FLDI0
FMOV
FNEG
FRm,FRn
DRm,FPUL
FRm,FRn
FR0,FRm,FRn
DRm,DRn
FRm,FPUL
FCMP/EQ
FCNVSD
FLOAT
FMUL
FSQRT
FSUB
#imm3,@(disp12,Rn)
SR,@-Rn
Rm,@(R0,Rn)
R0,@Rn+
R0,@(disp,Rn)
Rm,@-Rn
R0,@(disp,GBR)
Rm,@Rn
Rm,@(disp12,Rn)
GBR,@-Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rm,Rn
FRn
DRm,DRn
FRn
FRm,FRn
FPUL,DRn
FPUL,DRn
DRm,DRn
DRn
FRm,FRn
Rev. 3.00 Jul 08, 2005 page 480 of 484
REJ09B0051-0300