SH-2A Datasheet, PDF (366/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.5 Effect of Memory Load Instruction on Pipeline
With an instruction that performs a load from memory, return of data to the destination register is
performed in the WB stage at the end of the pipeline. Looking at such a load instruction
(designated “load instruction 1” here) and the instruction immediately following it (designated
“instruction 2”), the EX stage of instruction 2 comes before the WB stage of load instruction 1.
If, in this case, the destination register of load instruction 1 is used by instruction 2, since the
contents of that register have not yet been prepared, execution of the ID stage is delayed for a
period equivalent to the latency of instruction 1. The same also applies if the destination register
of load instruction 1 is the same as the destination, rather than the source, of instruction 2.
Similarly, execution of the ID stage is stalled for an additional slot if the destination of load
instruction 1 is the status register (SR) and a flag in SR is fetched and used by instruction 2 (such
as ADDC, for example).
When this kind of register contention occurs, the slot in which the destination register can be used
is the cycle after completion of the MA stage of instruction 1. This is illustrated in figure 8.34.
Therefore, if program is written in which an instruction that uses the result of a load instruction is
placed immediately after that load instruction, execution speed will decrease. Generally, the
latency of a load instruction is 2, and therefore speed will not decrease if an instruction that uses
the result of a load is placed 3 or 4 instructions after the load instruction. If a memory access
instruction is executed as a preceding instruction, the applicable number of instructions is 4 or
more, and if executed as a succeeding instruction, 3 or more.
Load instruction 1 (MOV.W @R0,R1) IF ID EX MA WB
Instruction 2
(ADD R1,R3)
IF — — ID EX
IF — ID EX
IF — — ID EX
Figure 8.34 Effect of Memory Load Instruction on Pipeline
Rev. 3.00 Jul 08, 2005 page 352 of 484
REJ09B0051-0300