SH-2A Datasheet, PDF (132/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.16 JSR/N
Jump to SubRoutine with No delay slot
Branch to Subroutine Procedure with No Delay Slot
Branch Instruction
SH-2A/SH2A-FPU (New)
Format
JSR/N @Rm
JSR/N @@(disp8, TBR)
Abstract
PC - 2→ PR, Rm → PC
PC - 2 → PR, (disp×4+TBR) → PC
Code
0100mmmm01001011
10000011dddddddd
Cycle
3
5
T Bit
―
―
Description
Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR
and execution branches to the address indicated by the contents of general register Rm as 32-bit
data or to the address read from memory address (disp × 4 + TBR). The stored contents of PC
indicate the starting address of the second instruction after the present instruction. This instruction
is used with RTS as a subroutine procedure call.
Notes
This is not a delayed branch instruction.
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4) as displacement values.
Rev. 3.00 Jul 08, 2005 page 118 of 484
REJ09B0051-0300