SH-2A Datasheet, PDF (414/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(6) Double-Precision Multiply Instruction (General Register Return)
Instruction Type
MULR R0,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm mm WB
IF — ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after six stages: IF, ID, mm, mm, mm, WB. mm indicates a state in which the
multiplier is operating.
See section 8.7, Contention Due to Multiplier, for general pipeline details. This instruction has
two execution slots, a latency of four, and two lock states. Detailed examples where there are
consecutive instructions relating to the pipeline of this instruction or the multiplier are given
below.
(a) When a MULR instruction is immediately followed by a MAC.W or MAC.L instruction
There is no multiplier contention.
MULR R0,Rn
MAC.L @Rm+,@Rn+
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm mm WB
IF — ID EX MA MA mm mm mm
IF — — — ID EX ⋅ ⋅ ⋅
Rev. 3.00 Jul 08, 2005 page 400 of 484
REJ09B0051-0300