SH-2A Datasheet, PDF(175/501 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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SH-2A Datasheet, PDF (175/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

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6.4.4

AND

Logical AND

AND logical

Section 6 Instruction Descriptions

Logical Instruction

Format

AND Rm,Rn

AND #imm,R0

AND.B #imm, @(R0,GBR)

Abstract

Rn & Rm â Rn

R0 & imm â R0

(R0 + GBR) & imm â (R0 + GBR)

Code

0010nnnnmmmm1001

11001001iiiiiiii

11001101iiiiiiii

Cycle T Bit

1

â

1

â

3

â

Description

Logically ANDs the contents of general registers Rn and Rm, and stores the result in Rn. The

contents of general register R0 can be ANDed with zero-extended 8-bit immediate data. 8-bit

memory data pointed to by GBR relative addressing can be ANDed with 8-bit immediate data.

Note

After AND #imm, R0 is executed and the upper 24 bits of R0 are always cleared to 0.

Rev. 3.00 Jul 08, 2005 page 161 of 484

REJ09B0051-0300

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