SH-2A Datasheet, PDF (36/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 3 Exception Handling
3.3 Address Errors
3.3.1 Address Error Sources
Address errors occur in instruction fetches and data read/write accesses, as shown in table 3.5.
Table 3.5 Bus Cycles and Address Errors
Type
Bus Cycle
Bus Master
Bus Cycle Operation
Address Error
Occurrence
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
No error (normal)
Address error
Instruction fetched from other than on-chip
peripheral module space^*
No error (normal)
Instruction fetched from on-chip peripheral
module space^*
Address error
Instruction fetched from external memory
space in single-chip mode
Address error
Data
CPU or
read/write DMAC
Word data accessed from even address
Word data accessed from odd address
No error (normal)
Address error
Longword data accessed from longword
boundary
No error (normal)
Longword data accessed from other than
longword boundary
Address error
Double longword data accessed from double No error (normal)
longword boundary
Double longword data accessed from other
than double longword boundary
Address error
Word data or byte data accessed in on-chip
peripheral module space^*
No error (normal)
Longword data accessed in 16-bit on-chip
peripheral module space^*
No error (normal)
Longword data accessed in 8-bit on-chip
peripheral module space^*
No error (normal)
External memory space accessed in single-
chip mode
Address error
Note: * For details of the on-chip peripheral module space, see the Bus State Controller section of
the hardware manual for the relevant product.
Rev. 3.00 Jul 08, 2005 page 22 of 484
REJ09B0051-0300