SH-2A Datasheet, PDF (403/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(10) PREF Instruction
Instruction Type
PREF
@Rm
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after four stages: IF, ID, EX, MA. There is no WB stage as there is no return of
data to the register.
Instruction Issuance
This instruction uses the memory access pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 389 of 484
REJ09B0051-0300